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MK32VT1632-10YC (98.09.03)
Semiconductor
MK32VT1632-10YC
16,777,216 Word x 32 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK):
DESCRIPTION
The Oki MK32VT1632-10YC is a fully decoded, 16,777,216 x 32bit synchronous dynamic random access memory composed of eight 64Mb DRAMs (8Mx8) in TSOP packages mounted with decoupling capacitors on a 168-pin glass epoxy Dual-in-Line Package supports any application where high density and large capacity of storage memory are required, like for example PCs or servers.
FEATURES
* * * * * * * * 16-Meg Word x 32-bit (2Bank 4Byte) organization 100-pin Dual Inline Memory Module All DQ Pins have 10 Damping Resister Single 3.3V power supply, 0.3V tolerance Input :LVTTL compatible Output :LVTTL compatible Refresh : 4,096 cycles/64 ms Programmable data transfer mode * /CAS latency (2, 3) * Burst length (2, 4, 8) * Data scramble (sequential, interleave) /CAS before /RAS auto-refresh, Self-refresh capability Serial Presence Detect (SPD) With EEPROM
* *
PRODUCT ORGANIZATION
Product Name Operation Frequency (Max.) 100 MHz Access Time (Max.) tAC2 tAC3 9.0ns 9.0ns
MK32VT1632-10YC
Note. Specification are subject to change without notice.
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MK32VT1632-10YC (98.09.03)
BLOCK DIAGRAM
CKE1 CKE0 /CS0 DQMB0 DQ0 DQ7 DQMB1 DQ8 DQ15 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 /CS1 /CS2 DQMB2 DQ16 DQ23 DQM /CS CKE DQ0 DQM /CS CKE DQ0 /CS3
1
DQ7 DQ7
5
DQ7
3
DQ7
7
DQMB3 DQ24 DQ31 DQM /CS CKE DQ0 DQM /CS CKE DQ0
2
DQ7 DQ7
6
DQ7
4
DQ7 Serial PD SCL
8
9
A0 A1 A2 SA0 SA1 SA2
SDA
1 2
CLK0 CLK1
5 6 7 8
3 4
/RAS,/CAS,/WE A0-A11,BA0,BA1
1
a
Vcc
8
SDRAMs Vss 0.22uF x8
Note. The Value of all resistors is 10.
MODULE
OUTLINE
(Front) (Back)
1 51
6 7 56 57
22 23 72 73
50 100
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MK32VT1632-10YC (98.09.03)
PIN CONFIGURATION
Front side Pin No. Pin name 1 VSS 2 DQ0 3 DQ1 4 DQ2 5 DQ3 6 VCC 7 DQ4 8 DQ5 9 DQ6 10 DQ7 11 DQMB0 12 VSS 13 A0 14 A2 15 A4 16 A6 17 A8 18 A10 19 BA1 20 NC 21 VCC 22 NC 23 NC 24 NC 25 CLK0 Back side Pin No. Pin name 51 VSS 52 DQ8 53 DQ9 54 DQ10 55 DQ11 56 VCC 57 DQ12 58 DQ13 59 DQ14 60 DQ15 61 DQMB1 62 VSS 63 A1 64 A3 65 A5 66 A7 67 A9 68 BA0 69 A11 70 NC 71 VCC 72 /RAS 73 /CAS 74 NC 75 CLK1 Front side Pin No. Pin name 26 VSS 27 CKE0 28 /WE 29 /CS0 30 /CS2 31 VCC 32 NC 33 NC 34 NC 35 NC 36 VSS 37 DQMB2 38 DQ16 39 DQ17 40 DQ18 41 DQ19 42 VCC 43 DQ20 44 DQ21 45 DQ22 46 DQ23 47 VSS 48 SDA 49 SCL 50 VCC Back side Pin No. Pin name 76 VSS 77 NC 78 NC 79 /CS1 80 /CS3 81 VCC 82 NC 83 NC 84 NC 85 NC 86 VSS 87 DQMB3 88 DQ24 89 DQ25 90 DQ26 91 DQ27 92 VCC 93 DQ28 94 DQ29 95 DQ30 96 DQ31 97 VSS 98 SA0 99 SA1 100 SA2
Pin Name Vcc Vss CLK# /CS# CKE# A0-A11 BA0, BA1 /RAS /CAS
Function Power Supply (3.3V) Ground (0V) System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe
Pin Name /WE DQMB# DQ# SDA SCL SA# N.C
Function Write Enable Data Input / Output Mask Data Input / Output Data I/O for SPD CLK input for SPD Socket Position Address for SPD No Connection
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MK32VT1632-10YC (98.09.03)
SERIAL PRESENCE DETECT
Byte No.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 72 73-90
SPD Hex Value 80 08 04 0C 09 02 20 00 01 A0 90 00 80 08 00 01 0E 04 06 01 01 00 06 F0 90 00 00 1E 14 1E 3C 08 30 10 30 10 00-00 02 33 41, 45, 20, 20, 20, 20, 20, 20 01 / 06
Remark Defines the number of bytes written into SPD memory Total number of bytes of SPD memory Fundamental memory type Number of rows Number of columns Number of module banks Data width of this assembly ... Data width continuation Voltage interface level Cycle time (CL=3) Access time from CLK (CL=3) DIMM configuration type Refresh rate / type Primary SDRAM width Error checking SDRAM width Minimum CLK delay Burst lengths supported Number of banks on each SDRAM /CAS latency /CS latency /WE latency SDRAM module attributes SDRAM device attributes : General Cycle time (CL=2) Access time from CLK (CL=2) Cycle time (CL=1) Access time from CLK (CL=1) Minimum ROW pulse width /RAS to /RAS bank delay /RAS to /CAS delay Minimum /RAS precharge time Density of each bank on module
Command and address signal input setup time Command and address signal input hold time
Notes 128 byte 256 byte SDRAM 12 rows 9 columns 2 bank 32 bits 0 LVTTL CL=3 tCC3=10ns CL=3 tAC3=9ns None Parity Normal / Self x8 tCCD: 1 CLK 2, 4, 8 4 banks 2, 3 0 0
Data signal input setup time Data signal input hold time SPD data revision code Checksum for byte 0-62 Manufacturer's JEDEC ID code Manufacturing location Manufacturer's part number Revision code R.F.U Intel specification frequency Intel specification /CAS latency Unused storage locations
CL=2 tCC2=15ns CL=2 tAC2=9ns Not support Not support tRP=30ns tRRD=20ns tRCD=30ns tRAS=60ns 32MB 3ns 1ns 3ns 1ns R.F.U 0.2
4D,4B,33,32,56,54,31,36,33, 32,2D,31,30,59,43,20,20,20 20, 20 91, 92 00-00 93-125 66 126 06 127 FF-FF 128-255
MK32VT1632-10YC
66MHz CL=2, 3
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MK32VT1632-10YC (98.09.03)
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating Voltage on any pin relative to Vss Vcc supply voltage Storage temperature Power dissipation Short circuit current Operating temperature Symbol VIN, VOUT Vcc, VccQ Tstg PD* IOS Topr Value -0.5 to Vcc+0.5 -0.5 to 4.6 - 55 to 125 8 50 0 to 70 Unit V V C W mA C
*: Ta=25C
Recommended Operating Conditions
Parameter Power supply voltage Input high voltage Input low voltage Symbol Vcc, VccQ VIH VIL Min. 3.0 2.0 -0.3 Typ. 3.3 (Voltages referenced to Vss = 0V) Max. Unit 3.6 Vcc+0.3 0.8 V V V
Capacitance
Parameter Input capacitance (A0-A11, BA0, BA1, /RAS, /CAS, /WE) Input capacitance (/CS0, /CS1, /CS2, /CS3) Input capacitance (DQMB0-DQMB3) Input capacitance (CKE0, CKE1) I/O capacitance (DQ0-DQ31) Input capacitance (CLK0, CLK1) (Vcc = 3.3V 0.3V, Ta = 25C f =1MHz) Symbol Max. Unit CIN1 40 pF CIN2 20 pF CIN3 10 pF CIN4 20 pF CI/O 14 pF CCLK 50 pF
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MK32VT1632-10YC (98.09.03)
DC CHARACTERISTICS
(Vcc = 3.3V 0.3V, Ta = 0 to 70C) Parameter Output High Voltage Symbol Condition CKE Others IOH = 2.0mA IOL = 2.0mA Module Spec. Min.
2.4
Max. -
Unit V
Note
VOH
VOL Output Low Voltage 0.4 V ILI Input Leakage Current -80 80 uA Output Leakage ILO -20 20 uA Current tCC=min. Average Power Supply tRC=min. ICC1 CKE VIH Current 620 mA (Operating) No Burst Power Supply Current tCC=min. ICC2 CKE VIH 320 mA (Stand by) Average Power tCC=min. ICC3S CKE VIL Supply Current 220 mA (Clock Suspension) Average Power CKE VIH, tCC=min. ICC3 Supply Current 480 mA /CS VIH (Active Stand by) Power Supply tCC=min. ICC4 CKE VIH Current 780 mA (Burst) Power Supply tCC=min. ICC5 CKE VIH Current 900 mA tRC=min. (Auto-Refresh) Average Power tCC=min. ICC6 Supply Current CKE 0.2V 16 mA (Self-Refresh) Average Power tCC=min. ICC7 Supply Current 16 mA CKE VIL (Power down) Notes: 1. Measured with the output open. 2. Address and data can be changed once or not be changed during one cycle. 3. Address and data can be changed once or not be changed during two cycle.
1, 2 3 2
3
1, 2
2
MODE SET ADDRESS KEYS
/CAS Latency A6 0 0 0 0 1 1 1 1 Note: Burst Type Burst Length BT=1 Reserved 2 4 8 Reserved Reserved Reserved Reserved A5 A4 CL A3 BT A2 A1 A0 BT=0 0 0 Reserved 0 Sequential 0 0 0 Reserved 0 1 Reserved 1 Interleave 0 0 1 2 1 0 2 0 1 0 4 1 1 3 0 1 1 8 0 0 Reserved 1 0 0 Reserved 0 1 Reserved 1 0 1 Reserved 1 0 Reserved 1 1 0 Reserved 1 1 Reserved 1 1 1 Reserved A7, A8, A10, A11, BA0, BA1 and All should stay "L" during mode set cycle.
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MK32VT1632-10YC (98.09.03)
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and enter the system clock. 2. After the Vcc voltage has reached the specified level, take a pause of 200s or more with the input being NOP. 3. Enter the precharge all bank command. 4. Apply CBR auto-refresh eight or more times. 5. Enter the mode register setting command.
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MK32VT1632-10YC (98.09.03)
AC CHARACTERISTIC
Parameter Clock Cycle Time Access Time from Clock Clock "H" Pulse Time Clock "L" Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock /RAS Cycle Time /RAS Precharge Time /RAS Active Time /RAS to /CAS Delay Time Write Recovery Time /RAS to /RAS Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time /CAS to /CAS Delay Time (Min) Clock Disable Time from CKE Data Output High Impedance Time from DQMB Data Input Mask Time from DQMB Data Input Time from Write Command Data Output High Impedance Time from Precharge Command Active Command Input Time from MODE Register Set Command Input (Min) Write Command Input Time from Output CL=3 CL=2 CL=3 CL=2 Symbol tCC tAC tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR tRRD tREF tPDE tT ICCD ICKE IDOZ IDOD IDWD IROH IMRD IOWD (Vcc = 3.3V 0.3V, Ta = 0 ~70C) NOTE 1, 2 Module Spec. Unit Note Min. Max. 10 15 3 3 3 1 3 3 90 30 60 30 15 20 tSI+1CLK 1 1 2 0 0 2 3 2 9 9 8 100,000 64 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle .
3, 4 3, 4
3
NOTES: 1) AC measurements assume tT=1ns. 2) The reference level for timing of input signals is 1.4V. 3) This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF (RLoad is 50ohm). 4) An access time is measured at 1.4V. 5) If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL. 1.4v 50 OUTPUT OUTPUT LOAD 50pF
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MK32VT1632-10YC (98.09.03)
FUNCTION TRUTH TABLE (Table1) (1/2)
Current State Idle /CS H L L L L L L L H L L L L L L H L L L L L L L H L L L L L L L H L L L L L L H L L L L L L /RAS X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L /CAS X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L /WE X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X BA X X BA BA BA BA X L X X BA BA BA BA X X X BA BA BA BA BA X X X BA BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 X RA, A10 X Action NOP NOP 2 ILLEGAL 2 ILLEGAL Row Active 4 NOP 5 Auto-Refresh or Self-Refresh Mode Register write NOP NOP Read Write 2 ILLEGAL Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Burst Stop 3 Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 2 ILLEGAL Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Burst Stop 3 Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 2 ILLEGAL 3 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL ILLEGAL
Row Active
Read
Write
Read with Auto Precharge
Write with Auto Precharge
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MK32VT1632-10YC (98.09.03)
FUNCTION TRUTH TABLE (Table1) (2/2)
Current State Precharge /CS H L L L L L L H L L L L L L H L L L L L L H L L L L H L L L L /RAS X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L /CAS X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X /WE X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X BA X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X Action NOP Idle after tRP NOP Idle after tRP 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 4 NOP ILLEGAL NOP NOP 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL NOP Row Active after tRCD NOP Row Active after tRCD 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL NOP Idle after tRC NOP Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL
AE AE
Write Recovery
Row Active
Refresh
AE AE
Auto Resister Access
ABBREVIATIONS
RA = Row Address CA = Column Address BA = Bank Address AP = Auto Precharge NOP = No Operation command
Notes: 1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of tCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle.
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MK32VT1632-10YC (98.09.03)
FUNCTION TRUTH TABLE (CKE) (Table2)
Current State (n) Self Refresh CKEn-1 H L L L L L L H L L L L L L H H H H H H H H L H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X H L L L L L L X X X X X /RAS X X H H H L X X X H H H X X X X H H H L L L X X X X X /CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X /WE X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self Refresh) INVALID Exit Power Down ABI Exit Power Down ABI ILLEGAL ILLEGAL 6 ILLEGAL NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension
AE AE
Power Down
AE AE
All Banks idle (ABI)
6
Any State Other than Listed Above
Notes:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
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